Using dynamic random access memories ("DRAMs") for a high performance main memory for a computer system is often less expensive than using static random access memories ("SRAMs"). Nevertheless, DRAMs are typically much slower than SRAMs.
A common technique for lessening the impact of slow DRAM access time on main processor performance is to employ a cache memory. A cache memory is a limited size fast memory, usually made up of SRAMs, which stores blocks of data, known as lines, that reflect selected main memory locations. A cache memory is smaller than the main memory it reflects, which means the cache memory typically is not fully addressable and must store a tag field for each data line. The tag field identifies the main memory address corresponding a particular data line.
When the main processor issues a read request and an address corresponding to desired data stored in main memory, the cache memory is checked by comparing the received address to the tag fields of the cache memory. If the desired data is stored in the cache, then a "hit" occurs and the desired data is immediately available to the main processor. If the desired data is not stored in the cache, then a "miss" occurs, and the desired data must be fetched from slower main memory. The typical goal in a cache memory design is to increase the hit rate because a low hit rate slows main processor performance.
One prior technique for increasing the hit rate in a cache memory subsystem is to use a prefetch buffer along with a main cache. A prefetch buffer is a memory that stores data prefetched from main memory. Data is speculatively prefetched into the prefetch buffer before a next read request based upon a prediction of the address for the next read request. When the main processor issues the next read request, the desired data may be available from the prefetch buffer if the prediction was accurate. In typical prior art systems, if the prediction was correct, the desired data is moved from the prefetch buffer to the main cache and is supplied to the main processor.
Nevertheless, prior art prefetch schemes that store prefetched data in the main cache often require relatively large main cache memories in order to maintain a high hit rate because the main cache typically becomes cluttered with predictable addresses, which are typically sequential. Unfortunately, larger cache memories increase the cost of the computer system and often preclude placement of effective caches on-chip with the main processor.